Integrated circuits (ICs) have become increasingly complex, requiring more input/output (IO) pins and operating current on smaller die sizes. In wire-bonded IC packages, it becomes difficult to balance IO, current, and die size requirements. Notably, a smaller die size yields less area for bond pads that can be used for IO. It is well known that, independent of the function being implemented, the minimum area of a wire-bonded IC is determined by the number of bond pads that must be instantiated along its periphery and the minimum pitch of such bond pads. Further, some of the bond pads must be used for “overhead” (i.e., not for user-defined IO), such as for power supply. With a silicon-technology-driven trend towards lower power-supply voltages, the supply current has had to rise even faster than an increasing need for power. Since the current-carrying capability of a bond wire has not increased, the number of power-supply bond pads has risen dramatically, yielding even less bond pads for IO use. Similarly, package pins have a limited current carrying capability. Consequently, the higher power-supply currents have also increased the number of package pins that must be set aside for the power supply, reducing the number of pins available for other purposes. Therefore, designers are forced to implement the IC in a wire-bonded package with less IO pins, increased die size, increased supply voltage, and/or reduced power consumption than desired.
Accordingly, there exists a need in the art for an integrated circuit package arrangement that overcomes the aforementioned deficiencies.